Photoresist defined features include copper pillars and redistribution layer wiring such as bond pads and line space features for integrated circuit chips and printed circuit boards. The features are formed by the process of lithography where a photoresist is applied to a substrate such as a semiconductor wafer chip often referred to as a die in packaging technologies, or epoxy/glass printed circuit boards. In general, the photoresist is applied to a surface of the substrate and a mask with a pattern is applied to the photoresist. The substrate with the mask is exposed to radiation such as UV light. Typically the sections of the photoresist which are exposed to the radiation are developed away or removed exposing the surface of the substrate. Depending on the specific pattern of the mask an outline of a circuit line or via may be formed with the unexposed photoresist left on the substrate forming the walls of the circuit line pattern or vias. The surface of the substrate includes a metal seed layer or other conductive metal or metal alloy material which enables the surface of the substrate conductive. The substrate with the patterned photoresist is then immersed in a metal electroplating bath, typically a copper electroplating bath, and metal is electroplated in the circuit line pattern or vias to form features such as pillars, bond pads or circuit lines, i.e., line space features. When electroplating is complete, the remainder of the photoresist is stripped from the substrate with a stripping solution and the substrate with the photoresist defined features is further processed.
Pillars, such as copper pillars, are typically capped with solder to enable adhesion as well as electrical conduction between the semiconductor chip to which the pillars are plated and a substrate. Such arrangements are found in advanced packaging technologies. Solder capped copper pillar architectures are a fast growing segment in advanced packaging applications due to improved input/output (I/O) density compared to solder bumping alone. A copper pillar bump with the structure of a non-reflowable copper pillar and a reflowable solder cap has the following advantages: (1) copper has low electrical resistance and high current density capability; (2) thermal conductivity of copper provides more than three times the thermal conductivity of solder bumps; (3) can improve traditional BGA CTE (ball grid array coefficient of thermal expansion) mismatch problems which can cause reliability problems; and (4) copper pillars do not collapse during reflow allowing for very fine pitch without compromising stand-off height.
Of all the copper pillar bump fabrication processes, electroplating is by far the most commercially viable process. In the actual industrial production, considering the cost and process conditions, electroplating offers mass productivity and there is no polishing or corrosion process to change the surface morphology of copper pillars after the formation of the copper pillars. Therefore, it is particularly important to obtain a smooth surface morphology by electroplating. The ideal copper electroplating chemistry and method for electroplating copper pillars yields deposits with excellent uniformity, flat pillar shape and void-free intermetallic interface after reflow with solder and is able to plate at high deposition rates to enable high wafer through-out. However, development of such plating chemistry and method is a challenge for the industry as improvement in one attribute typically comes at the expense of another. This is especially true when copper pillars having relatively large diameters and heights are being plated. Such copper pillars are typically referred to as megapillars and may have heights from 50 μm up to and exceeding 200 μm. To achieve such dimensions copper pillars are electroplated from plating baths at high plating rates from 5 Amps/dm2 and higher, typically from 20 Amps/dm2 and higher. At such high plating rates pillars electroplated from many conventional copper electroplating baths develop nodule defects and irregular surface morphology. Such nodule defects and irregular surface morphology can compromise performance of electronic articles in which the pillars are included. Copper pillar based structures have already been employed by various manufacturers for use in consumer products such as smart phones and PCs. As Wafer Level Processing (WLP) continues to evolve and adopt the use of copper pillar technology, there will be increasing demand for copper electroplating baths and methods with advanced capabilities that can produce reliable copper megapillar structures.
Accordingly, there is a need for copper electroplating baths and methods which provide copper photoresist defined features such as copper pillars where the features have substantially uniform surface morphology and are capable of electroplating megafeatures at high electroplating rates with reduced or no nodule development.